Low power has been one of the key themes of TSMC Reference Flow in the pervious years. In Reference Flow 9.0, we bring you more leading-edge low power features including dynamic power reduction with advanced clock gating technique and low power clock-tree synthesis capability, new standby leakage power reduction features, and the support for both power specification standards, Common Power Format (CPF) and Unified Power Format (UPF). All these features are developed in the latest TSMC 40nm technology and help reduce chip power consumption, extend battery life for portable devices, and reduce system packaging and cooling costs.

Transparent Half-Node Design Support

Reference Flow 9.0 delivers transparent half-node designs, eliminating the need for designers to define the half-node scaling factor multiple times in different tools throughout whole design cycle in order to migrate a design from a full node to 'shrink' node by traditional design flows. Designers can use Reference Flow 9.0 to start chip design using 45nm rules, and transparently target the design toward 40nm without explicitly dealing with a multitude of scaling factors.

Enhanced Statistical Static Timing Analysis (SSTA)

Reference Flow 8.0 introduced the first foundry design methodology to include intra-die statistical timing analysis along with statistical leakage and statistical timing optimization. To further improve setup and hold timing margins, Reference Flow 9.0 now supports stage-based on-chip variation, as well as design-specific on-chip variation derived from statistical analysis. In addition, new transistor-level path-based statistical static timing analysis (SSTA) is introduced to enhance timing accuracy and reduce the need for pre-characterized cell libraries. These features enable designers to reduce excess design margins, optimize design performance and increase yields.

Design for Manufacturing (DFM)

Reference Flow 9.0 provides significant improvements in both physical and electrical DFM capabilities to speed up DFM analysis for large designs and address potential parametric performance shifts caused by DFM effects. Reference Flow 9.0 offers hierarchical DFM analysis for all three physical DFM effects: LPC, CMP and CAA, significantly reducing design iterations, accelerating DFM analysis, and improving accuracy when DFM information is annotated to the design abstracts.

Electrical DFM improvements include table-based DFM-LPE extraction flow for faster extraction turnaround, while maintaining the accuracy of the model-based DFM approach. Shape-to-Electrical (S2E) and Thickness-to-Electrical (T2E) DFM engines are now silicon-based models, which improves the accuracy of the predicted electrical performance of the design. Hierarchical analysis capability and more accurate DFM models shorten design cycles by enabling designers to anticipate DFM issues and take necessary measures to improve design robustness and increase yields.

Need further information about TSMC Reference Flow? Please log in to TSMC-Online^SM, and click on "Reference Flow" under the Design Portal 2.0 category.

Please contact Andrew Wu (email address: andrew_wu@tsmc.com ) should you have questions, suggestions, and comments.