Since 2004, TSMC has succeeded to ramp the Nexsys^SM 90nm process in TSMC's state-of-the-art 12-inch fab, Fab12, located in Hsinchu, Taiwan. In 2005, TSMC has also completed to qualify Fab14 in Tainan. There are hundreds of product tape-outs and hundreds of thousands 12�� wafer shipment since first tape-out. And TSMC develops DFM to help Customers achieve better yield performance thru volume production data. TSMC boasts a significant advantage in its combination of 90nm process technology with 12-inch wafers, which produces significant economic gains. In addition, the half node process 80GC (1.0/3.3V) was also released in Q4, 2006. 80GC can achieve better standby and active power than 90G while reducing die area by more than 10%, depending on the non-shrinkable IP module ratio. 80GC can be used in many product applications including consumer, network and computer product segments

Nexsys^SM technology satisfies the power, performance and integration requirements of a broad spectrum of applications and includes high-performance, low-power, mixed-signal/RF, embedded DRAM, and non-volatile memory options. TSMC established the Nexsys^SM brand for its next-generation SoC process technology platform. The company's 90-nm technology is the first TSMC process to adopt this brand. Nexsys^SM offers a unique triple gate oxide option that facilitates three different oxide thicknesses on a single chip. The triple gate oxide feature removes design restrictions caused by various core/IO combination requirements and should lead to more innovative SoC designs. With 70-75% linear shrinkage and a 2X performance improvement, compared to TSMC's 0.13-Micron technology, Nexsys^SM is poised to become the de-facto SoC process technology platform standard.

	The 90-nm process technology features:
	Core supply voltage ranging from 1.0V to 1.2V I/O and analog blocks ranging from 1.8V to 3.3V Multiple threshold voltage (Vt) option for optimized transistor speed and power consumption trade-offs Extremely tight process control for 50-nanometer gate length - the high speed process Ni-salicide for better sheet resistance (Rs) in narrow line widths Nine-layer copper interconnect, with an extra redistribution layer optional for flip-chip package Low-k dielectrics with k less than 2.9 for the lowest RC delay and power consumption
	NexsysSM mixed signal/RF process features:
	MiM capacitor High resistance resistor High Q inductor and varactor DNW(deep N well) bipolar junction transistor